This invention relates, in general, to a method of forming a buried contact in a semiconductor wafer substrate. More particularly, a sublithographic contact is formed using a removable spacer which has improved etching selectivity in relation to an underlying insulator oxide layer in a semiconductor wafer.
In semiconductor structures wherein a capacitor is used as a storage element, such as seen in Dynamic Random Access Memory (DRAM) devices, it is necessary to connect the access transistor active area to the capacitor bottom plate (storage plate). This connection is known as a buried contact, i.e., other layers or elements are above the contact surface. Typically, buried contacts are no smaller than the lithographic minimum associated with patterning the wafer.
In order to reduce the cost and increase the speed of operation, memory devices have become increasingly more miniaturized. To that end, each individual component of the semiconductor structure must occupy less space on the device. However, because the capacitance of a capacitor is proportional to the area of the electrodes, to operate efficiently, the overall size of the capacitor must be maintained or a new type of improved capacitor must be employed. Notwithstanding the fact that various new types of capacitors have been recently introduced (e.g., trench and stacked capacitors) limitations in the possible level of capacitor miniaturization necessitates modifying other surrounding structures, such as contact surfaces and buried contact areas, in order to decrease the overall size of the semiconductor device.
With the aforementioned shortcomings in mind, it would be advantageous to provide a method of reducing the size of a semiconductor device (or substructures therein) by forming a sublithographic buried contact which: reduces the cell area; improves the capacitor storage plate registration alignment; provides a smaller buried contact area that intercepts alpha particles such that soft error rate is improved; improves the subthreshold voltage characteristics by moving the buried contact edge away from the access transistor; and facilitates formation of a contact that is self-aligned in both directions so that a single, large, rectangular mask can be used to etch a plurality of buried contacts.
According to principles of the present invention, a removable spacer, such as ozone tetraethyl orthosilicate (O3TEOS), is used to reduce the size of a contact opening between polysilicon word lines below a lithographic minimum. The removable spacer is deposited before the patterning and forming of a buried contact and is selected from a material having higher etching selectivity than the materials forming the underlying structures and layers, such as the underlying insulator oxide layer.
Since word lines diverge at the location of a DRAM cell where a buried contact exists, the removable spacer is deposited so that it does not completely fill the gap created by the divergence of the word lines, but does fill more narrow gaps at other locations between the word lines. In essence, the divergent area comprises a lesser amount of spacer O3TEOS than other, more narrow gap areas between the word lines. Accordingly, during a removal step (e.g., by etching), the etchant penetrates the lesser amount of O3TEOS at the buried contact area to create the sublithographic buried contact, but does not penetrate other areas where a thicker layer of O3TEOS has filled in the narrow gaps between word lines.
The removable spacer reduces the buried contact size since the actual self-aligned contact area is defined by the spacer sidewall. An opening smaller than a lithographic minimum is etched because silicon oxide surrounding the buried contact area is protected by the removable spacer. The removable spacer is removed after the resist strip, leaving a small buried contact opening.
More specifically, the invention describes a method for forming a removable spacer having an improved etching selectivity in relation to an underlying insulator oxide of a semiconductor wafer. Other objects, advantages, and capabilities of the present invention will become more apparent from the following detailed description with reference to the accompanying drawings.
The invention also describes semiconductor assemblies formed according to the aforementioned methods.